FIG. 8 of the attached drawings is an arrangement view of a conventional information processing system which is shown in "Realization Technique Of Hyperparallel Machine" published in Information Processing (Vol. 32, No. 4, PP 367, 1991), for example. In FIG. 8, the reference numeral 61a-61c denote processors; 62a-62c, memories connected respectively to the processors 61a-62c; 63, a uniform inter-coupling network (global bus) which has the memories 62a-62c and by which the processors 61a-61c are connected to each other through local buses 64a-64c. The memories 62a-62c, connected to each other by the inter-coupling network (global bus) 63, form a distributed-type covalent memory.
Operation will next be described. The processors 61a-61c are operable independent of each other. However, it is required that all the processors 61a-61c execute an operation as a unified whole. Processing will proceed while the running states of the respective related processors 61a-61c are held. An exchange of running-state information between the processors 61a-61c is realized by the use of the memories 62a-62c, through the inter-coupling network (global bus) 63. When a processor 61a-61c executes a transmission through the inter-coupling network 63 (global bus), a transmitting processor name and running-state information serve as transmitted data. The receiving processor decodes the transmitted data, and recognizes the identity and running state of the transmitting processor.
The conventional running-state information transmitting apparatus for the multiprocessing system, constructed as described above has the following problems. Specifically, since each of the processors 61a-61c are required to transmit the running-state information separately from each other, a lot of time is required for transmittal processing of the running-state information for transmission. In addition, since the inter-coupling network is occupied during transmission of the running-state information, the time allotted for original processing is reduced so that throughput of the system is lowered. Further, since a recognition of the running state of the transmitting processor is executed by-software processing a considerable amount of processing time at the receiving side processor is required.